Post silicon validation engineer
$108,000–$172,800 year
On-site · Austin, Texas, United States or San Jose, California, United States
Job Summary
Post-Silicon Validation Engineer to drive bring-up, characterization, and debugging of our next-generation Ethernet and PCIe Retimer chips. Focus on advanced Ethernet PHY validation to ensure silicon meets IEEE networking standards and high-speed interoperability requirements. Key responsibilities include hands-on bring-up of multi-rate Retimer ICs, validating Ethernet (100G/400G/800G) and PCIe (Gen5/6) for IEEE and PCI-SIG compliance, building Python-based automated test frameworks for Ethernet throughput, BER, and control path testing with ARM-based micros and GPIO/MDIO/I2C protocols; network debugging to root-cause silicon, link training, and firmware bugs using protocol analyzers and traffic generators. Educational requirements include a Bachelor's in Engineering with 8+ years or a Master's in Engineering with 6+ years of related experience. Salary range: $108,000-$172,800 per year. Benefits include discretionary bonus and equity, medical/dental/vision, 401(k) with company match, ESPP, EAP, paid holidays, sick leave, and vacation, with equal opportunity employment statements.
Required Qualifications
- Bachelors in Engineering and 8+ years of related experience or Masters degree in Engineering and 6+ years of related experience
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