Physical Verification Engineer

Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction, resolves complex verification challenges across advanced CMOS processes, drives quality improvements in design kits and documentation, and develops best practice guidelines for physical verification flows. The role includes leading optimization of verification methodologies (DRC, LVS, ERC, PERC), delivering customer-facing technical support and training, collaborating with internal teams and customers, and driving adoption of advanced verification techniques for 22nm and below CMOS processes. The position offers direct customer engagement, opportunities to influence foundry verification toolchains (ICV, Calibre, Pegasus, StarRC/Quantus/xACT), and a hybrid work model across US sites (Phoenix, Santa Clara, Hillsboro). The role requires strong analytical problem-solving, effective communication, and the ability to provide technical direction to engineering teams while ensuring successful customer tape-outs and design flow optimization.