Physical Design - SOC Top Lead
On-siteSan Jose, Texas, United States
Job Summary
Lead full-chip integration, timing closure, and power planning for next-generation SoCs, managing floorplanning, macro placement, and convergence across hierarchical blocks. Own physical verification, signal integrity, clock tree strategy, and DFT integration to drive tapeout readiness and GDS handoff. Coordinate package/IO co-design and manage cross-team tradeoffs between block owners, DV, and architecture. Mentor engineers on convergence best practices and establish flow standards for chip-top closure. Requires 8-12+ years of physical design experience with multiple full tapeouts, deep hands-on expertise in advanced nodes, and tool fluency in Innovus, Tempus, and Calibre. Join the newly formed hardware engineering group to shape the future of edge computing.
Required Qualifications
- Master's degree in Electrical Engineering
- 5+ years of industry experience
- PhD in Electrical Engineering
- 3+ years of industry experience
- 8-12+ years of physical design experience
- at least 2-3 full tapeouts at the chip-top/SoC integration level
- Deep hands-on experience with advanced nodes
- Proven track record owning full-chip timing closure across multiple corners/modes on a complex SoC
- Strong PDN/IR-drop/EM analysis experience
- Voltus or equivalent
- Experience with chip-level DFT integration
- scan stitching
- MBIST
- JTAG
- Tool fluency: Innovus (or ICC2)
- Tempus/PrimeTime
- RedHawk
- Calibre
- Demonstrated ability to lead technically without direct reports
- driving alignment across multiple engineers and teams on convergence decisions
- Comfortable operating with significant ownership and ambiguity in a small, fast-moving team
- solve problems rather than hand off convergence problems
- Excellent scripting skills in TCL, shell and python
Desired Qualifications
- Familiarity with package co-design
- flip-chip/BGA
- C4 bumps
- ball map
- Knowledge of computer architecture
- Knowledge of physical design and ASIC implementation
- Experience in full chip sign off convergence
- Knowledge of circuit design
- device physics
- deep sub-micron technology
- its implications to physical design
- Proficiency with industry-grade physical design flow
- Experience in integrating analog or mixed-signal macro on top-level design
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