Physical Design (PD) Solution Architect
$35,000–$45,000 year
On-siteBengaluru, Karnataka, India
Job Summary
Lead physical implementation strategy, methodology definition, PPA optimization, and implementation planning for complex SoCs. Serve as the technical authority for physical design architecture, feasibility analysis, and successful project delivery across global teams. Drive tape-outs on advanced technology nodes (10nm and below) using Synopsys ICC2, Fusion Compiler, and Cadence Innovus, while managing large SoCs exceeding 100M gates. Ensure mastery of floorplanning, CTS, timing closure, power optimization, and signoff methodologies with mandatory experience in TSMC nodes, UPF, multi-voltage designs, and AI-based EDA tools like DSO or Cerberus. Manage HBM/HMC memory systems integration within this C2-level role in Bangalore, offering up to ₹45 LPA for 9+ years of experience.
Required Qualifications
- experience in Physical Design
- Multiple successful tape-outs on advanced technology nodes (10nm and below)
- Floorplanning
- CTS (Clock Tree Synthesis)
- Timing Closure
- Power Optimization
- Synopsys ICC2
- Fusion Compiler
- Cadence Innovus
- UPF and multi-voltage designs
- large SoCs (>100M gates)
- signoff methodologies
- TSMC technology nodes
- AI-based EDA tools such as DSO or Cerberus
- HBM/HMC memory systems
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