Physical Design Engineer
On-site · Catania, Sicily, Italy
Job Summary
Implement ASIC physical design flow including floorplanning, placement optimization, clock tree synthesis, routing, and physical verification. Optimize designs for performance, reliability, and manufacturability. Perform chip-level power integrity analysis across multiple voltage domains (IR drop, electromigration). Work on digital implementation embedded in analog environments. Collaborate with global cross-functional teams including analog designers and verification engineers. Requires experience in ASIC Physical Design with strong knowledge of floorplanning, placement, CTS, routing, and sign-off checks, and power integrity analysis. An analog layout background is a plus; team-oriented, international collaboration is valued. Renesas is an embedded semiconductor solution provider with a diverse, global footprint and a focus on flexible, inclusive work environment including remote options.
Required Qualifications
- Experience in ASIC Physical Design
- Strong understanding of floorplanning, placement, CTS, routing, and sign-off checks
- Knowledge of power integrity analysis (IR drop and electromigration)
- A team player who enjoys working in an international, collaborative environment
- Analog Layout experience is a plus
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