Physical Design Engineer II (Silicon Engineering)
On-site · Austin, Texas, United States or Irvine, California, United States
Job Summary
Develop and implement next-generation ASIC physical design for SpaceX Starlink systems. Responsibilities include partition synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, and signoff checks; collaborate with ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs; resolve design/timing/congestion issues, identify potential solutions and drive execution; run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop; requires 3+ years RTL2GDSII physical design, experience with EDA tools, knowledge of FinFET/CMOS physics, DFT/MBIST/LBIST, and scripting; ITAR compliance and ability to work extended hours.
Required Qualifications
- Bachelor’s degree in electrical engineering, computer engineering or computer science
- 3+ years of professional RTL2GDSII physical design and/or physical design flow development
- Experience with industry standard EDA tools
- Knowledge of deep sub-micron FinFET and CMOS solid state physics
- Understanding of CMOS digital design principles and standard cells
- Understanding of CMOS power dissipation in deep submicron processes
- Familiar with CMOS analog circuit and physical design
- Basic knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows
- Good scripting skills (csh/bash, Perl, Python, TCL, Makefile)
- Ability to work extended hours and weekends as needed
- ITAR requirements: U.S. citizen or permanent resident or eligible to obtain required authorizations
Additional Requirements
- ITAR compliance: U.S. citizen or national, permanent resident, refugee or asylee, or eligible to obtain authorizations
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