Physical Design Engineer II (IC)
$87,400–$165,000 year
On-siteSan Jose, California, United States
Job Summary
Execute synthesis, place and route, and static timing analysis for assigned ASIC chip partitions while adhering to strict schedules. Collaborate with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues, driving electromigration and IR verification alongside logical equivalence checking. Refine physical design methodologies for synthesis, power delivery networks, and timing convergence, while troubleshooting flow issues with EDA vendors. Requires 7+ years of hands-on experience in physical design, proficiency in Innovus, Tempus, and Quantus, and strong TCL scripting skills. Located in San Jose, California, this full-time engineering services role offers an annual range of $87,400 to $165,000.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience
- 7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification
- Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus
- Deep understanding of physical design flows and methodologies
Desired Qualifications
- 7+ years of experience in physical design roles and related activities
- Proven ability to adhere to tight schedules and implement low-power design techniques
- Experience in System-on-Chip (SoC) design and implementation
- Expertise in sub-7nm node technologies
- Familiarity with industry-standard EDA tools and their capabilities
- Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys
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