Physical Design Engineer
$150,000–$250,000 year
On-site · San Jose, California, United States or Irvine, California, United States
Job Summary
Lead full-chip Physical Verification efforts and drive execution plans/schedules for full-chip PV. Own full-chip PV verification, coordinate with analog and PD teams to ensure manufacturability and tapeout readiness, and provide early guidance on corner case requirements. Partner with analog, block, and chip-top owners to influence floorplan constraints and implementation strategy; conduct PV checks (DRC/ERC/LUP/PERC) and interpret results using ICV/Calibre on advanced TSMC nodes; leverage Tcl/Python/shell scripting for automation to support PV workflows; drive quality, milestones, and tapeout readiness across multiple programs.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering or related field
- 5+ years of experience with full chip verifications
- Proven hands-on experience with Physical Verification tool (ICV/Calibre)
- Able to assemble a flow to support block/chip level PV
- Strong expertise in Floorplanning to avoid DRC/LVS issues
- Provide guidance to analog IP team to allow for clean integration
- Experience with using either ICV or Calibre verification tools
- Understanding advance TSMC DRC rules
- Cross-Functional Collaboration with analog, block, chip top owners to ensure clean floorplan
- Participate in tapeout readiness reviews
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