Physical Design Engineer
HybridVancouver, British Columbia, Canada
Job Summary
Lead engineer driving PPA improvements for critical graphics blocks by serving as the main point of contact between Physical Design and RTL teams. Study block microarchitecture and data flow to determine optimal memory placement and Synthesis/P&R recipes, while collaborating with RTL designers to resolve frequency, LOL, and timing bottlenecks early in the project cycle. Partner with Methodology and CAD teams to optimize tools and flows, delivering best-known recipes to PD tile owners and analyzing standard cell library offerings for PPA impact. Provide mentorship to junior and senior engineers while navigating ambiguity to drive results across 3nm, 5nm, 7nm, and 16nm SOC taping projects.
Required Qualifications
- Bachelor's or Masters degree in computer engineering/Electrical Engineering
- Experience in ASIC Physical Design from RTL to GDSII
- Strong RTL analysis skills including Verilog, Timing Analysis, and library understanding
- Strong knowledge in design margining methodology, low voltage design, silicon – STA correlation
- Hands on experience in taping out 3nm, 5nm, 7nm and/or 16nm SOC
- Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
- Must be a self-starter, and be able to independently and efficiently drive tasks to completion
- #LI-LC3
- #LI-HYBRID
Desired Qualifications
- Experience in ASIC Physical Design from RTL to GDSII
- Strong RTL analysis skills including Verilog, Timing Analysis, and library understanding
- Strong knowledge in design margining methodology, low voltage design, silicon – STA correlation
- Hands on experience in taping out 3nm, 5nm, 7nm and/or 16nm SOC
- Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
- Strong communication, time management, and presentation skills
- Excellent analytical, problem solving, and attention to detail skills
- Provide mentorship and guidance to junior and senior engineers, and be an effective team player
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