Physical Design Engineer, AI Accelerator IP
$100,000–$500,000 year
HybridAustin, Texas, United States
Austin, Texas, United StatesHybridFull Time$100,000–$500,000 yearSenior LevelDoctorate Or Professional DegreeAI HardwareMedium
Full TimeSenior LevelDoctorate Or Professional DegreeMediumAI Hardware
Job Summary
Own physical implementation of AI accelerator IP blocks end to end, from synthesis through PnR, timing closure, and GDSII signoff. Drive PPA outcomes by closing critical paths with RTL owners and delivering hardened deliverables on advanced nodes for external licensees. Build floorplans, power grids, and clocking strategies while managing multi-variant IP delivery across foundries and process nodes. Front-to-back co-design with architecture, RTL, and chiplet teams to directly impact customer deal timelines. This role requires a track record of tapeouts and expertise in tools like Innovus and PrimeTime.
Required Qualifications
- BS/MS/PhD in EE/ECE/CE/CS
- 5+ years of block-level or IP-centric physical design through tapeout
- Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime)
- Expertise with scripting languages (Tcl, Python, Perl)
- Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC)
- Experience building floorplans, power grids, pin placement, and clocking strategies
- Experience delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports)
- Eligible to access U.S. export-controlled technology
- Eligible to obtain prior license approval from the U.S. Commerce Department or applicable federal agency
Desired Qualifications
- Track record of block-level and IP tapeouts on advanced nodes
- Driven by PPA outcomes
- Rigorous about signoff quality
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.