Physcial Design Engineer
On-siteBengaluru, Karnataka, India
Job Summary
Own the end-to-end physical design flow from netlist to final sign-off, including chip-level floorplanning, placement, clock-tree synthesis, routing, timing closure, and physical verification. Execute PNR activities using Cadence Innovus to optimize performance, power, area, and signal integrity while resolving congestion and timing violations. Collaborate with cross-functional teams to drive root-cause analysis on complex physical design challenges and support design reviews. Mentor junior engineers and contribute to improving physical design methodologies and automation. Drive implementation across multiple stages to ensure smooth progression toward sign-off on advanced semiconductor designs.
Required Qualifications
- 10+ years of hands-on experience in semiconductor physical design and implementation
- Strong expertise in the complete PNR/physical design flow
- Extensive experience with Cadence Innovus and related physical implementation tools
- Strong understanding of floorplanning, placement, CTS, routing, optimization, and timing closure
- Deep knowledge of STA, including setup/hold analysis and timing optimization
- Strong understanding of physical design constraints and their impact on power, performance, and area (PPA)
- Experience debugging congestion, timing, placement, routing, and clock-related issues
- Strong understanding of semiconductor design flows and interaction between RTL, synthesis, STA, DFT, and physical implementation
- Ability to independently own complex blocks or projects and drive them through implementation and closure
- Strong analytical and problem-solving skills with excellent attention to detail
- Effective communication and collaboration skills with cross-functional engineering teams
- Ability to mentor engineers, contribute to methodology improvements, and take technical ownership of challenging physical design problems
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