Padring Verification Engineer
On-siteHsinchu, Taiwan, Taiwan
Job Summary
Develop scalable padring verification methodologies, tools, and automation for RTL integration, connectivity verification, and chip assembly. Execute padring verification and connectivity signoff for GPU and Tegra projects, analyzing results, debugging failures, and driving issues to closure. Verify DFT-related padring logic including boundary scan, test-access connectivity, and control configuration. Define verification plans, develop assertions, checkers, testbenches, and coverage goals. Build flows that identify integration issues early and apply AI-assisted approaches to debug challenges. Collaborate with RTL, DFT, Physical Design, CAD, Package Design, and Software teams to resolve complex issues and meet project milestones.
Required Qualifications
- MS in Computer Engineering, Electrical Engineering, or equivalent practical experience
- 1–8 years of experience in ASIC/SOC design, RTL verification, SOC integration, or methodology development
- Strong understanding of RTL and SOC verification concepts, including simulation, formal checks, assertions, coverage, regressions, debug, and signoff
- Familiarity with DFT concepts, particularly boundary scan, JTAG/test-access mechanisms, scan/test modes, or padring DFT integration
- Experience creating verification environments, checkers, or automation for SOC- or subsystem-level designs
- Proficiency in Python, Perl, or other industry-standard scripting languages
- Excellent analytical, problem-solving, communication, and cross-functional collaboration skills
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