Package Layout Design Senior Staff Engineer
On-site · Bengaluru, Karnataka, India
Job Summary
Senior Staff Engineer in High-speed IC package development responsible for driving microelectronic package development from concept through tapeout, collaborating with package architects and technical leads to select technologies and ensure manufacturability, performance, reliability, and cost compliance. Responsibilities include developing C4 and BGA ball maps optimized for SI/PI and layout efficiency; planning and validating netlist mappings across dies, interposers, and substrates; defining die placement, padstacks, net assignments, and package-level connectivity; creating and maintaining Package Requirement Documents detailing die arrangements, stackups, and design constraints. Requires experience with large, complex packages, netlists/schematics, and cross-functional teamwork; proficiency with Cadence OrbitIO/ISP; strong understanding of packaging design rules, SI/PI fundamentals, and advanced packaging architectures (CoWoS, EMIB, CPO, CPC); familiarity with 2D/2.5D packaging, thermal/mechanical constraints, and automation scripting; ability to communicate, present, and document design decisions; willingness to learn and collaborate across global teams; export control considerations and compliance. Additional compensation and benefits information provided by the employer.
Required Qualifications
- Previous experience developing netlists and schematics for large, complex packages
- Previous experience developing C4 and BGA ball maps for high-pin-count designs
- Proficiency with Cadence OrbitIO / Integrity System Planner (ISP) or equivalent
- Strong foundational understanding of package design, including design rules, breakout, place and route, signal shielding, reference planes, power distribution, and pinout optimization across package and system requirements
- Solid grasp of SI/PI fundamentals at the substrate, board, and system levels; familiarity with running and interpreting signal and power simulations is a plus
- Knowledge of 2D, 2.5D, and emerging packaging architectures such as CoWoS-S/R/L, EMIB, CPO, and CPC
- High-level understanding of thermal and mechanical package constraints (e.g., warpage, TIM)
- Experience contributing to tool, process, and flow development, including library maintenance and basic scripting for automation
- Familiarity with foundry design rules and substrate manufacturing constraints
- Demonstrated ability to work across cross-functional teams and global time zones
- Strong interpersonal skills and willingness to learn
- Experience collaborating with chip and board design and electrical simulation teams to optimize package and system co-design
- Experience collaborating with chip and board design, and electrical simulation teams for co-design and optimization
- Strong communication, presentation, and documentation skills
- Export control awareness (EAR) and compliance considerations
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