MTS DRAM ASIC Architect
On-siteBengaluru, Karnataka, India
Job Summary
Define next-generation DRAM + logic-die architectures, including functional partitioning between DRAM arrays, peripheral circuitry, and advanced CMOS logic die platforms to optimize performance, power, cost, reliability, and product differentiation. Identify and evaluate system, interface, reliability, test, management, and control functions that may benefit from advanced logic-die implementations; perform architectural tradeoff analysis covering area, power, latency, yield, testability, reliability, and product scalability. Architect high-performance interfaces between DRAM die and logic die, including command, data, clocking, synchronization, test, monitoring, and management paths. Lead cross-functional technical discussions across DRAM design, ASIC architecture, packaging, process technology, product engineering, validation, firmware, and system architecture teams to drive tradeoff-based decision making.
Required Qualifications
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related discipline
- 5+ years of experience in semiconductor architecture, design, or system engineering
- Experience in one or more of the following areas: DRAM architecture, memory subsystem architecture, ASIC/SoC architecture
- Good understanding of DRAM architecture including command flows, timing behavior, bank architecture, refresh management, row hammer mitigation, reliability features, and memory subsystem operation
- Exposure to high-speed I/O, PHY architectures, clocking systems, SI/PI considerations, power delivery, thermal design, and/or die-to-die interfaces
- Demonstrated ability to lead cross-functional technical discussions, develop architectural proposals, and drive tradeoff-based decision making
- Strong analytical and problem-solving skills
- Ability to drive architecture tradeoff studies across multiple engineering disciplines
- Excellent written and verbal communication skills
Desired Qualifications
- Experience with DDR5/DDR6, LPDDR5/LPDDR6, HBM, GDDR, or emerging memory technologies with strong understanding of memory protocols, timing architectures, memory training, calibration, and PHY design
- Experience evaluating architectural tradeoffs across DRAM die, logic die, advanced packaging, and system-level implementations
- Experience with die-to-die interconnect technologies including TSV-based architectures, hybrid bonding, 2.5D/3D packaging, stacked-die systems, and advanced memory integration
- Strong knowledge of CMOS technologies, semiconductor device fundamentals, analog/mixed-signal circuit concepts, and memory interface design
- Understanding of SI/PI, clocking, power delivery, thermal considerations, and heterogeneous integration challenges
- Experience working with industry standards organizations, customers, or ecosystem partners related to memory technologies
- Experience with HBM base die architectures, embedded controllers, advanced memory system features, RAS, security, or logic-die-based memory products
- Proven ability to leverage AI-assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies
- Leverage AI tools to automate the tools and workflow
- Applying Artificial Intelligence in workflows to improve build efficiency
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