ML Architect, Hardware Software Co-Design (All Levels)
$206,000–$258,000 year
On-sitePalo Alto, California, United States
Job Summary
Research state of the art perception models and lead development of optimizations for mapping quantized models (e.g., CNNs, Transformers) to embedded and heterogeneous hardware platforms. Design and implement hardware-aware optimizations including quantization strategies, model compression, and operator fusion targeted to custom accelerators. Collaborate with hardware teams to co-optimize model architecture and compute pipelines under real-time constraints while benchmarking system performance across platforms. Partner with perception, systems, and autonomy teams to align model efforts with the hardware roadmap and real-world autonomy requirements.
Required Qualifications
- Ph.D. or M.S. in Computer Engineering, Electrical Engineering, Computer Science, or related field with a focus on ML compilers, embedded systems, or hardware-aware AI
- Hands-on experience with quantized model deployment, ML design stacks, and code generation for embedded or heterogeneous compute systems
- Strong understanding of computer vision models (e.g., object detection, segmentation) and their optimization for edge inference
- Proficiency in deep learning frameworks (e.g., PyTorch, TensorFlow) and their low-level IRs or export formats (e.g., ONNX)
- Solid programming skills in C++, Python
- Familiarity with CUDA/OpenCL (or other accelerator programming models)
Desired Qualifications
- Prior experience working with hardware-software co-design, especially for autonomous or robotics platforms
- Deep knowledge of numerical precision trade-offs, quantization-aware training (QAT), and dynamic/static quantization flows
- Familiarity with embedded real-time constraints and hardware profiling/debugging tools
- Familiarity with rearchitecting models to best suit hardware capabilities
- Publication record in top-tier ML/Systems conferences (e.g., MLSys, NeurIPS, DAC, ICCAD)
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