Mixed Signal Design Verification Engineer
HybridBengaluru, Karnataka, India
Job Summary
Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure compliance with design specifications. Develop comprehensive IP verification plans, test benches, and environments to achieve thorough coverage of mixed signal microarchitecture specifications. Define and execute verification plans, running system simulation models, analyzing power and timing, and identifying design bugs. Debug failing tests in the presilicon environment through root cause analysis and implement corrective measures. Collaborate with digital and analog architects, RTL developers, and physical design teams to improve architectural features. Lead technical reviews of test plans and validation proofs while documenting findings. Maintain and refine functional verification methodologies, infrastructure, and tools to keep pace with industry advancements. This role supports Intel's leadership in delivering best-in-class computing solutions through rigorous validation of cutting-edge IPs.
Required Qualifications
- Bachelor's or Master's degree in Electronics, VLSI Engineering, or a related field
- 4-12 years of experience with a Bachelor's degree, or 3-10 years of experience with a Master's degree in ASIC or SoC verification
- Excellent knowledge on DDR4/DDR5/LP5/LP6 protocol
- Expertise in System Verilog, UVM, and Verilog for mixed signal verification
- Hands-on experience with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium/JasperGold, or Mentor Questa
- Strong scripting skills in Python, Perl, or Tcl for testbench automation and process efficiency
- In-depth knowledge of standard protocols including JTAG, IJTAG, CRI, and APB, as well as multi-clock domain mixed signal designs
- Proficiency in constraint-random test generation, root cause analysis, and debugging of complex mixed signal designs
- Ability to thrive in a dynamic, multidisciplinary team environment
Desired Qualifications
- Experience with low-power design techniques, including UPF and clock gating, to optimize power consumption
- Familiarity with Formal Property Verification tools and version control systems such as Git or Perforce
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