(Mid/Sr/Princ) Verification Design Engineer (UVM)
On-siteSunnyvale, California, United States
Job Summary
Create UVM testbench environments interfacing with Digital AMS and software, developing infrastructure, testbenches, tests, and coverage to ensure proper functionality and zero bug escapes. Design, develop, and maintain modular, reusable UVM testbenches for Celestial ML custom blocks while collaborating with ASIC and software design teams to develop test plans. Confirm test completeness through code and functional coverage, providing technical leadership and mentoring. This role supports iterative HLS-generated code verification within the novel Celestial AI architecture, requiring a BSEE with 3+ years of UVM experience and strong Python integration skills.
Required Qualifications
- 3+ years of experience with UVM Testbench Infrastructure
- In depth knowledge of UVM testbenches, stimulus, constraints, and testing
- Extensive experience with System Verilog, Python, and some experience with C/C++
- Experienced with random testbench implementation, code and functional coverage
- Self-motivated with strong technical skills
- Great team player
- Effective communicator
- History of high quality first silicon success
- BSEE +4 years relevant experience
- MSEE
Desired Qualifications
- Prefer extensive knowledge of Python test infrastructure integrating Jenkins, git, JIRA
- Experience with PCIE, AXI-4, ARM standards beneficial
- Experience with formal verification preferred
- Some knowledge of ML, AI trends, and HW accelerator landscape, preferred
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