Mid Level ASIC Design Engineer
On-siteSunnyvale, California, United States
Sunnyvale, California, United StatesOn-siteFull TimeMid LevelStartup
Full TimeMid LevelStartup
Job Summary
Author micro-architecture specifications and implement complex Verilog RTL designs for high-performance convolutional neural network accelerators. Integrate CPU and third-party IP blocks into the SoC subsystem while collaborating with verification engineers to achieve code coverage closure. Resolve implementation and timing issues with the physical design team to optimize power, and perform diagnostic and post-silicon validation tests to assist with software bring-up. Requires 3+ years of ASIC design experience in RTL logic and IP integration, with proficiency in front-end tools and low-power UPF flows.
Required Qualifications
- 3+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog
- Experience in IP integration, specifically CPU IP into SoC
- Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
- Familiarity with AMBA/APB/AXI Protocol
- Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C
- Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies
- Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains
- B.S. (M.S. preferred) degree in Electrical or Computer engineering
Desired Qualifications
- Previous experience with timing closure at high frequencies
- Interest to explore AI architectures for convolution, transformer and other kinds of workloads
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