Memory Validation Architect
$209,500–$303,000 year
On-siteSan Jose, California, United States
Job Summary
Define and own the end-to-end validation architecture and strategy for memory subsystems across multiple FPGA product families, driving planning from architecture definition through silicon bring-up and customer deployment. Architect scalable validation frameworks and reusable infrastructure supporting DDR5, LPDDR5/LPDDR6, and HBM technologies, while establishing methodologies for functional correctness, performance characterization, reliability stress testing, and error recovery. Lead pre- and post-silicon validation for memory controllers and PHYs, manage complex root-cause investigations involving RTL, firmware, and signal integrity, and collaborate with board design and DRAM vendors to optimize channel topology and ensure interoperability. Mentor engineering teams and champion AI-driven validation to improve productivity. This role offers a unique opportunity to define the future of memory validation for industry-leading FPGA products.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
- 15+ years of industry experience in memory subsystem architecture, silicon validation, high-speed interface development, or a related field
- Master's degree with 13+ years of related industry experience
- Ph.D. with 10+ years of related industry experience
- 10+ years of hands-on experience designing, validating, debugging, or optimizing DDR memory technologies, including DDR4, DDR5, LPDDR4, LPDDR5, HBM, or newer JEDEC-compliant memory standards
- 10+ years of experience with at least four of the following: Memory controller architecture or DDR PHY architecture or Memory initialization and training or DDR calibration algorithms or JEDEC memory specifications or Memory timing analysis and scheduling
- 8+ years of experience leading or contributing to silicon bring-up, silicon debug, characterization, validation, and production qualification for complex SoCs or memory subsystems
- 8+ years of experience performing board-level signal integrity (SI), power integrity (PI), timing analysis, or high-speed memory channel validation
- 5+ years of hands-on experience using high-speed laboratory validation equipment such as oscilloscopes, protocol analyzers, logic analyzers, Bit Error Rate Testers (BERTs), traffic generators, or equivalent debugging tools
- 5+ years of programming or automation experience using Python, C/C++, or similar scripting or programming languages to develop validation, debug, characterization, or test automation solutions
- 5+ years of experience leading cross-functional technical projects involving at least three of the following disciplines: architecture, RTL design, firmware, silicon validation, software development, customer engineering, or product engineering
- Applicants must be eligible for any required U.S. export authorizations
- Must be eligible for any required U.S. export authorizations
Desired Qualifications
- Experience with FPGA or ASIC memory subsystem development
- Expertise in HBM, CXL Memory, Compute Express Link, or emerging memory technologies
- Experience working with major DRAM vendors including Micron, Samsung, and SK hynix
- Strong understanding of PCIe, CXL, AXI, AMBA, and coherent interconnect architectures
- Experience defining organization-wide validation methodologies and automation frameworks
- Demonstrated success influencing architecture decisions across multiple product generations
- Experience leading globally distributed engineering teams and mentoring senior technical contributors
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