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SilvacoPosted 1 month ago
EXPIRED

Memory Senior Modeling Engineer

On-siteDa Nang, Da Nang City, Vietnam

Full TimeSenior LevelMasters DegreeMedium

Job Summary

Develop, generate, and maintain the full set of memory views and models for the SRAM, ROM, and Register-File portfolio, ensuring correctness and on-time delivery to Physical Design, Static Timing, and DFT teams. Validate timing and power Liberty models across PVT corners, build behavioral Verilog/SystemVerilog models, and run regression environments to guarantee specification compliance. Create and validate memory descriptions for Tessent MBIST, generate ATPG patterns with Synopsys TetraMAX, and build scan flows using Siemens/Mentor FastScan. Automate model-generation and QA flows using Perl, Python, TCL, and Shell to improve turnaround time. Provide mentorship to junior engineers and collaborate closely with design and CAD teams to support validation of fabricated silicon.

Required Qualifications

  • BS/MS in Electronics Engineering, Telecommunications, Microelectronics, Computer Engineering, Physics, or a related field
  • Minimum 4 years of hands-on experience in memory modeling, or DFT for IC/IP design
  • Liberty (.lib) timing & power model generation and validation (NLDM/CCS)
  • Memory behavioral Verilog/SystemVerilog model development
  • Verilog model testing, verification, and regression methodology
  • Tessent memory description and MBIST flows
  • Synopsys TetraMAX ATPG
  • Siemens/Mentor FastScan ATPG / scan
  • Strong scripting/programming skills (Perl, Python, TCL, Shell) on Unix/Linux
  • English Language Proficiency: Fluency, written and verbal
  • Strong communication, analytical, and problem-solving skills

Desired Qualifications

  • Master's degree in Electronics / Microelectronics Engineering
  • Hands-on experience with memory compilers and view-generation flows
  • Familiarity with CCS/NLDM characterization, SPICE correlation, and standard views (LEF, GDS, CDL)
  • Understanding of memory architectures (SRAM/ROM/Register File) and STA concepts
  • Experience with advanced FinFET process nodes
  • Knowledge of functional safety (ISO 26262) and quality (ISO 9001) processes

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