Memory Circuit Design Engineer

Memory Circuit Design Engineer responsible for partnering with domain experts to develop and deliver high-quality memory technology collateral and drive circuit innovations enabling next-generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS processes. Responsibilities include memory pathfinding with PPA optimization via design technology co-optimization (DTCO), memory bit-cell and periphery IC layout and automation, memory array/IP design, pre-Si verification and post-Si validation for yield and parametric tracking, and debugging to enable ramp. The Advanced Design team focuses on pathfinding and development of advanced memory technology to deliver best-in-class collateral, IP, and product design across Intel process generations. Requires extensive experience in custom memory circuit design, verification, and EDA tools, with a strong emphasis on DTCO and multi-physics optimization. Hybrid work model in the US (Oregon, Hillsboro). Posting to support consideration for employment without regard to race, color, religion, sex, national origin, age, disability, or other protected characteristics. The role contributes to Intel’s memory technology roadmap and collaboration with internal/external customers to accelerate time-to-market.