Mask Design Engineer
Hillsboro, Oregon, United StatesOn-siteContractMid LevelNot SpecifiedWarehousingUnknown
Job Summary
The Mask Design Engineer is responsible for layout design, verification, post-layout fixes, and sign-off of high-performance Analog and Mixed Signal blocks, including IO and High-Speed IO blocks. Key responsibilities include leading the Mask Design team for client engagement, interfacing with the Circuit Design team on-site, and ensuring proficiency in EDA tools like Cadence and Mentor Graphics. The role requires deep knowledge of Analog and Mixed Signal components, experience with deep sub-micron layout techniques, and expertise in verification checks and layout reliability analysis.
Required Qualifications
- At least 4 – 8 years’ experience in understanding and Independent handling of various Analog and Mixed Signal blocks such as LDO, Switching Regulators, Data Converters, PLL, SerDes, LVDS and top level layout integration of AMS blocks.
- Good Understanding of deep sub-micron layout techniques and issues in CMOS process technology nodes like 14nm, 22nm, 16nm FinFET technologies.
- Experience in Genesys / Genoa layout editor, Aapr flow, Helix etc.
- Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
- Deep understanding of reliability analysis in layout like EM, IR drop, latch-up, ESD etc using Apache tools.
- Should have good knowledge of CMOS, FinFET process and fabrication.
- Full-chip integration and verification experience.
- Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC), Hercules.
Desired Qualifications
- Knowledge of scripting languages such as Perl/Tcl and Skill is a plus.
- Good team player with excellent communication skills, interfacing with the circuit team