Manager, Package Design Engineering

Manager, Package Design Engineering at Astera Labs in San Jose leads and scales the Package Design team to deliver end-to-end IC packaging solutions—from concept through production ramp—supporting PCIe, CXL, and Ethernet connectivity with 2.5D/3D, chiplet, and heterogeneous integration. The role requires building and mentoring a high-performing team, establishing design standards, leading design reviews and issue resolution, and collaborating with SIPI, silicon architecture, board design, OSATs, and substrate vendors to ensure manufacturability and design feasibility across multiple product lines. Responsibilities include defining substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements, driving tradeoffs across performance, cost, yield, and schedule, and enabling scalable design methodologies and automation flows. Preferred experience includes advanced packaging architectures and scripting/workflow optimization.