Manager, Formal Verification
On-site · Shanghai, Shanghai, China
Job Summary
Lead and grow a team of formal verification engineers focused on pre-silicon Formal verification of complex digital designs. Define and drive formal verification strategies and methodologies to prove the correctness of designs across multiple projects. Collaborate closely with Architecture, Design, DV teams to identify verification needs and drive closure. Provide technical guidance, mentoring, and support to engineers in the team. Own the planning and execution of formal verification deliverables to ensure high quality and timely tapeouts.
Required Qualifications
- BSc or MSc in Electrical/Computer Engineering, Computer Science, or Mathematics
- 3+ years of managerial experience in a chip design or verification domain
- 8+ years of overall industry experience in formal verification, functional verification, or RTL design
- Deep understanding of formal verification concepts, tools, and flows
- Excellent leadership, problem-solving, and communication skills
- Strong analytical and debugging abilities
- Hands-on experience with formal verification (preferred)
- Background in developing formal testbenches, assertions, and coverage models (preferred)
- Managerial experience in chip design domain (preferred)
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