Logic Lead
On-sitePune, Maharashtra, India
Pune, Maharashtra, IndiaOn-siteFull TimeSenior LevelMasters DegreeLarge
Full TimeSenior LevelMasters DegreeLarge
Job Summary
Lead architectural design and FPGA implementation for next-generation wireless protocol analyzers, defining hardware accelerators for Bluetooth and Wi-Fi 7 capture engines. Develop RTL for high-speed bus interfaces and demodulators, optimizing resources for timing closure and throughput while mentoring engineers through the complete development lifecycle. Collaborate with RF boards, software drivers, and validation teams to debug live FPGA issues and support system integration. Requires 8+ years in digital RTL design with deep expertise in AMD Xilinx or Intel Altera architectures and SystemVerilog.
Required Qualifications
- Bachelor's or Master's degree in Electrical or Computer Engineering
- 8+ years in digital RTL design with a strong focus on FPGA deployment
- Expert-level mastery of SystemVerilog, Verilog, or VHDL
- Deep knowledge of high-performance AMD Xilinx (UltraScale+, Versal) or Intel Altera (Stratix/Agilex) architectures
- Deep understanding of Bluetooth (BR/EDR/LE) physical and link layers
- Experience with high-speed transceivers (GTY/GTY), PCIe, USB 3.0, and DDR4/DDR5 memory interfaces
- Familiarity with digital filters, mixers, and FFTs implemented in FPGA fabric
Desired Qualifications
- Experience building commercial test, measurement, or wireless sniffing equipment
- Expertise in advanced timing closure techniques for high-utilization FPGA designs
- Familiarity with Python, C/C++, or MATLAB for hardware modeling and automated testing
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