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Efficientcomputer3 months ago

Lead STA Engineer

$200,000–$250,000 year

On-site · Austin, Texas, United States or San Jose, California, United States

Type
Full Time
Level
Senior Level
Education
Masters Degree
Company size
Unknown

Job Summary

Lead STA Engineer to drive and develop timing flows and convergence for state-of-the-art finfet and multi-patterning based technologies from scratch using Cadence Tempus or Synopsys Primetime. Own and drive timing convergence of IP, Subsystem and SoC blocks. Define timing margining, PVTRC corner definitions, extraction methodology, and signoff timing to SYN/PNR correlation. Develop slew rate and glitch noise checks to ensure robust design quality. Develop custom timing checks for Efficient’s Ultra low power architecture. Collaborate with RTL, DFT and IP vendors to define and drive SDC constraints. Maintain an in-depth understanding of collaterals for all hard and soft IPs and coordinate with post-si/ pre-si teams for timing correlation. Coordinate with 3rd party vendor resources and work to improve flow consistency and efficiency across multiple product lanes. Position requires leadership in a cross-functional hardware engineering environment and experience with high-frequency, low-power ASIC timing. Compensation ranges from $200,000 to $250,000 plus equity and comprehensive benefits.

Required Qualifications

  • Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
  • Proven track record of delivering IP/SS (or SoC) STA sign-off for multiple tape-outs in 12nm or below process technologies
  • Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques
  • Hands-on experience in timing convergence of high-frequency and low power designs
  • Expert knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions and timing margining
  • Experience with low power implementation typical in industry and how timing convergence impacts power draw ensuring we are making optimal tradeoffs
  • Excellent scripting skills in TCL, shell and python
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$200k – $250k / yr

Lead STA Engineer · Efficientcomputer

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