Lead RTL Engineer ( Mixed-Signal IPs)
On-siteHyderabad, Telangana, India
Job Summary
Develop synthesizable, high-quality RTL for mixed-signal IPs including ADC/DAC interfaces, PLL/DLL control, power management units, and sensor front-ends. Collaborate with analog design engineers to define digital-analog interface specifications and ensure correct functionality through behavioral modeling, simulation, and co-verification. Participate in design reviews, micro-architecture definition, and documentation while performing design quality checks including lint, CDC, and synthesis readiness analyses. Integrate mixed-signal IPs into SoC top-level RTL and resolve functional or timing issues during full-chip validation. Contribute to continuous improvement of design methodologies, automation scripts, and reuse strategies for mixed-signal IP development.
Required Qualifications
- 5–10 years of experience in digital RTL design
- strong exposure to mixed-signal IP or subsystem development
- Proficiency in Verilog/SystemVerilog
- experience with synthesis and static verification flows (lint, CDC)
- Familiarity with analog/mixed-signal concepts such as signal sampling, clocking, calibration, and power management
- Good understanding of digital communication protocols (SPI, I2C, APB, AXI)
- Experience working in cross-functional environments involving analog, verification, and SoC integration teams
- B.E./B.Tech or M.S./M.Tech in Electrical Engineering, Electronics, or Computer Engineering
- Strong understanding of digital design and verification fundamentals
- Ability to work effectively across analog and digital domains in a collaborative environment
- Excellent debugging, problem-solving, and analytical skills
- Good communication and documentation abilities
Desired Qualifications
- Hands-on experience with mixed-signal co-simulation tools (Cadence AMS Designer, Synopsys VCS AMS, etc.)
- Exposure to scripting (Python, Perl, TCL) for automation and design flow enhancements
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