Lead RTL Engineer (CPU & Processor Design)
Hybrid · Austin, Texas, United States or Bengaluru, Karnataka, India
Job Summary
Lead RTL Engineer for CPU/processor design leading a team of 5-7 RTL engineers through the full design cycle, translating architecture specs into synthesizable SystemVerilog, owning RTL coding standards and timing closure, coordinating GDSII handoff with an outsource partner, and collaborating with verification and physical-design teams. Role combines hands-on RTL development with technical leadership, owning synthesis flow (Design Compiler or Genus), defining timing constraints (SDC), reviewing RTL submissions for correctness and synthesizability, and guiding tapeout-ready deliverables. Remote or Hybrid placement with a preference for Austin, TX or Bengaluru, India; contract-based long-term engagement with potential for FTE depending on country.
Required Qualifications
- 7+ years of RTL design experience using SystemVerilog
- Proven experience leading RTL development for processor, CPU, DSP, or datapath-intensive designs
- Experience delivering at least one silicon tapeout through GDSII handoff
- Strong synthesis and timing closure experience using industry-standard EDA tools
- Deep understanding of microarchitecture and hardware design principles
- Experience with advanced semiconductor process technologies (28nm or below preferred)
- Ability to lead engineering teams while remaining highly hands-on technically
- Strong communication and technical leadership skills
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