Lead Functional Product Engineer, Power Analysis
$114,800–$213,200 year
On-siteSan Jose, California, United States
San Jose, California, United StatesOn-siteFull Time$114,800–$213,200 yearSenior LevelEnterprise
Full TimeSenior LevelEnterprise
Job Summary
Develop and maintain Signoff power analysis flows by integrating them with synthesis and PnR stages. Reproduce, debug, and resolve customer-reported issues in power analysis tools while deploying and validating these flows at customer sites. Provide hands-on technical support to customers and collaborate to optimize power results and improve flow efficiency. Contribute to flow automation and scripting for repeatable deployments, documenting debug findings and best practices. Requires hands-on experience with Signoff power analysis, Verilog/SystemVerilog, and tools such as Joules or Voltus.
Required Qualifications
- Hands-on experience with Signoff power analysis (static and dynamic power)
- Knowledge of power optimization techniques in Synthesis (clock gating, operand isolation, multi-Vt cell selection)
- Working knowledge of UPF (Unified Power Format) — power domains, isolation, level shifting, retention
- Proficiency in Verilog/SystemVerilog for design analysis and testcase creation
- Understanding of digital design fundamentals — clock domains, pipeline stages, timing/power trade-offs
- Experience with low-power design methodologies (DVFS, power gating, multi-voltage)
- Familiarity with Liberty (.lib) and SPEF formats
- Scripting skills: Tcl, Python, or Shell
- Familiarity with tools such as Joules, Voltus, PTPX or equivalent
- B.E./B.Tech or M.E./M.Tech in Electronics / VLSI / Computer Engineering or equivalent
- Must have 3+ years of industry work experience
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