Lead Digital Verification Engineer

Lead Digital Verification Engineer to own end-to-end verification strategy for complex SoC/IP designs from specification through tapeout in a multi-block program. Define verification plans mapping specs to features, stimulus strategies, coverage goals, and sign-off criteria. Architect scalable UVM-based testbench environments with agents, scoreboards, reference models, and coverage monitors. Develop constrained-random stimulus for protocol interactions, concurrency, error injection, and corner cases. Define and close functional coverage models, deploy SystemVerilog Assertions across simulations, and drive full-chip verification including boot sequences, DMA flows, and multi-power-domain checks. Manage bug lifecycles, regression suites, CI/CD integration, and coordination with RTL, compiler, DFT, physical design, and post-silicon validation teams. Lead, mentor, and grow the verification team, represent readiness in tapeout sign-off reviews, and support gate-level simulations as part of design signoff. Requires 10+ years in ASIC/SoC verification, with at least 3 years in a lead role, and expertise in UVM, SystemVerilog, and verification methodologies. Competitive salary with equity and comprehensive benefits.