Lead DFT Engineer - MBIST
On-siteBengaluru, Karnataka, India
Job Summary
Lead DFT Engineer responsible for architecting, implementing, and validating advanced DFT solutions across complex SoCs, with emphasis on MBIST, SCAN insertion, ATPG, RTL/GLS verification, and collaboration with PnR. Role includes defining DFT architecture, leading scan insertion and pattern generation, MBIST integration for embedded memories, RTL-level DFT verification, GLS with SDF back-annotation, test protocol validation across modes, repair-signature integration, and support for silicon bring-up and manufacturing test strategies. Requires strong expertise in Tessent, SystemVerilog/UVM, scripting (Tcl/Python/Shell), and post-silicon diagnostics; location Bengaluru, Karnataka, India.
Required Qualifications
- BSEE/MSEE in Electrical Engineering with 10+ years of hands-on experience in JTAG, Scan, Memory BIST, and ATPG
- Proficiency in SystemVerilog and UVM-based verification environments
- Expertise with ATPG and MBIST tools, particularly Tessent (mandatory)
- Strong testbench development, simulation, and debug skills
- Experience in post-silicon failure analysis, diagnostics, and debugging
- Ability to work with ATE patterns and perform gate-level simulations
- Scripting and automation using Tcl, Python, and Shell
- Experience in RTL development and functional verification of logic circuits (added advantage)
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