Lead Debug/Trace/Profiling Design Engineer
On-site · Boston, Massachusetts, United States or Austin, Texas, United States
Job Summary
Lead the design and implementation of debug, trace and profiling hardware for high-performance RISC-V-based SOCs, architecting RTL generators and configurable hardware in a fast-paced environment; collaborate with architecture, performance, software and hardware teams to explore microarchitecture, integrate content into Chisel/FIRRTL, and contribute to verification plans, documentation, and customer/partner engagement.
Required Qualifications
- MS/PhD in EE, CE, CS or a related technical discipline
- 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high-performance processors
- Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL
- Knowledgeable in debug interfaces, JTAG, cJTAG
- Knowledgeable in CPU architectures, power management and SoC design
- Experience in debugging tools, profiling methods
- Knowledge of at least one object-oriented and/or functional programming language
- Knowledge of one or more of: Chisel/Scala, RISC-V architecture, Git/Jira/Confluence is a plus
- MS/PhD in EE, CE, CS or a related technical discipline
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