Lead ASIC Physical Design Engineer – Advanced Nodes
On-siteZürich, Zurich, Switzerland
Job Summary
Define and maintain a robust RTL-to-GDSII implementation flow, owning synthesis, floorplanning, partitioning, P&R, CTS, routing, and closure. Drive MCMM timing closure, power optimization, and ECO strategy while establishing constraint methodology, library strategy, and sign-off standards. Lead low-power implementation including UPF/CPF, isolation, and retention, integrating SRAMs and custom macros into mixed digital/custom environments. Ensure clean DRC/LVS, IR/EM, and reliability closure, then industrialize the backend flow with automation, CI, and reproducible builds. Build and mentor a growing physical design team to execute next-generation compute technology strategies.
Required Qualifications
- 10+ years in ASIC physical design
- 2+ successful tapeouts as implementation owner (block or subsystem level)
- Deep expertise in either a Synopsys or Cadence toolchain
- Strong MCMM STA & timing-closure experience
- Proven floorplanning & hierarchical integration capability
- Hands-on experience with IR/EM analysis & power grid planning
- Solid understanding of multi-voltage / power-gated designs
- Experience scripting for automation (Tcl, Python)
- Confidence making major implementation decisions independently
Desired Qualifications
- DFT exposure (scan, MBIST, test timing awareness)
- Experience at advanced FinFET nodes (7nm)
- Knowledge of EUV / multi-patterning considerations
- Familiarity of reliability-driven or safety-critical design standards
- Package / board-level awareness (power integrity, bump planning, thermal)
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