Lead ASIC Design Engineer
$143,800–$230,000 year
On-siteSan Jose, California, United States
Job Summary
Lead Chip Lead for next-generation silicon projects responsible for top-level digital architecture, microarchitecture, and full-chip integration. Drives cross-disciplinary alignment between Logic Design, Physical Design, Architecture, and Design Verification to meet PPA targets, owns tape-out sign-off, and provides architectural mentorship. Key duties include authoring and optimizing RTL/Synth blocks in SystemVerilog/Verilog, driving timing constraints (SDC), CDC strategy, front-end flows (synthesis, STA, CDC), IP management, silicon validation, and collaboration with post-silicon teams. Requires 12+ years of ASIC/SoC experience, expert SystemVerilog/Verilog design skills, proficiency with front-end EDA tools, and a proven tape-out track record. US work authorization is required. Compensation range: $143,800 - $230,000 with bonus and equity opportunities. Broadcom offers a comprehensive benefits package.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
- 12+ years of direct industry experience in ASIC/SoC digital design
- Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles
- Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites)
- Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies
- Outstanding documentation and verbal communication skills; capability to author architectural and design specifications
- Work Authorization: Must have legal authorization to work in the US
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