Junior FPGA Developer
$100,000–$175,000 year
On-siteChicago, Illinois, United States
Job Summary
Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency trading applications. Develop simulation testbenches and functional verification environments to validate FPGA designs before hardware deployment. Run synthesis, place-and-route, and static timing analysis; iterate on designs to meet strict timing constraints. Participate in hardware bring-up and on-board debugging using waveform analysis tools. Work closely with senior engineers to translate latency requirements into hardware design decisions. Leverage AI tools to accelerate development workflows including RTL review and debugging. Grow understanding of market data protocols like Ethernet and PCIe. Join a small team with direct access to founders, managing real P&L and building proprietary low-latency systems. Chicago-based role with full health coverage and a base salary of 100,000 - 175,000 USD.
Required Qualifications
- BS or MS in Electrical Engineering, Computer Engineering, or a related field
- Hands-on experience with RTL design in Verilog or SystemVerilog
- Familiarity with FPGA simulation tools (e.g., ModelSim, QuestaSim, Vivado, Quartus)
- Understanding of digital logic fundamentals: state machines, FIFOs, clock domain crossing, timing constraints
- Comfort working in a Linux environment
- Ability and eagerness to incorporate AI tools into your development and debugging workflow
- A strong desire to learn the HFT domain
Desired Qualifications
- Python, basic C or C++
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