Junior Engineer, FPGA

Junior Engineer, FPGA responsible for FPGA design using Verilog/VHDL/SystemVerilog and/or high-level synthesis to develop accelerated logic for FPGAs. The role involves parsing FPGA design files, integrating proprietary IP designs, reading/writing IP datasheets and documentation, and developing/maintaining testbenches. Candidate should have experience targeting FPGA boards (notably Xilinx), building timing-clean designs, managing multi-clock-domain and synchronization logic, and producing design documentation. Educational requirements include a Bachelor's or Master’s degree in Computer Engineering, Electrical Engineering, or ECE. Location is Princeton, NJ, onsite in the US.