IP Design Verification Engineer

IP Design Verification Engineer responsible for developing verification plans, test benches, and environments to ensure coverage of microarchitecture specifications; performing system-level simulations to validate functionality, timing, and power; identifying and debugging issues in pre-silicon environments; collaborating with architects, RTL developers, and design teams to improve verification processes; maintaining and improving verification infrastructure and methodologies; documenting verification plans and proofs; contributing to verification infrastructure and TFMs; utilizing IP test environments and validation tools to uncover design flaws. Requires strong analytical and problem-solving skills, effective cross-team communication, and staying current with industry trends in functional verification. Degree in Electrical or Computer Engineering with 4+ years (Bachelor's) or 3+ years (Master's) experience, proficiency with RTL and IP verification, and unrestricted permanent right to work in Mexico; role is hybrid in Guadalajara, Mexico.