IO and Memory Sub-Sytem Architecture
$180,000–$334,200 year
HybridSan Jose, California, United States
Job Summary
Lead architecture, design, and development of next-generation DRAM sub-system solutions for server and high-performance computing applications, including DDR6, LPDDR6, and HBM technologies. Drive technical decisions on memory interfaces, PHY architecture, signal integrity, and system integration while defining subsystem requirements and translating system-level needs into design specifications. Provide leadership across multidisciplinary teams comprising ASIC, PHY, firmware, validation, and platform engineering to execute systems bring-up, debug, characterization, and performance optimization. Define verification methodologies, lead root-cause analysis of complex design issues, and present technical proposals to engineering leadership and ecosystem partners. Translate JEDEC standards into product requirements and engage in customer discussions to ensure robust interoperability.
Required Qualifications
- Master's Degree (M.S.) in Electrical Engineering, Computer Engineering, or a related technical discipline
- 12+ years of industry experience in semiconductor, ASIC, memory, or high-speed interface development
- Demonstrated experience leading complex technical projects and influencing architectural decisions
- DDR5/DDR6/LPDDR5/HBM Memory Expertise
- High-Speed PHY Design
- Tx/Rx Circuit Architecture
- DFE/CTLE Equalization Techniques
- I2C, I3C, USB Interfaces
- Digital Design & Verification
- Technical Specification Development
- Analytical Problem Solving
- Executive-Level Presentations
- Must be able to spend an average of at least three days per week onsite
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