intern in AI System Verification

Develop a fully functional PCIe DIP and AVIP integration example to serve as a reference platform for customer bring-up and debug activities. Implement RTL wrappers, glue logic, and connection verification using Chipstack technology, potentially applying AI-based techniques for assertion generation. Configure TLM virtual platforms on the bus and CPU sides to run operating systems with PCIe drivers connected via AXI AVIP bridges. Explore debuggability mechanisms for Verisium Debug visualization and performance monitoring through SystemVIP/SPA for transaction analysis. Evaluate applicability of existing PCIe VIP to AVIP and consider extensions like Virtual Bridge or SpeedBridge integration.