IC Package Layout Team Leader
$210,600–$305,100 year
On-siteSan Jose, California, United States
Job Summary
Lead and support the San Jose package layout team, providing technical guidance, mentorship, and day-to-day oversight for layout engineers on complex ASIC packaging projects. Coordinate resource allocation and staffing across concurrent initiatives while collaborating with package leads, SI/PI teams, and manufacturing partners to resolve technical challenges. Optimize package pinouts, stack-ups, power distribution, and high-speed interface implementation, driving continuous improvement in methodologies and engineering efficiency. Contribute to hiring, onboarding, and development of engineering talent, aligning standards with the global layout organization.
Required Qualifications
- Bachelor's degree in Electrical Engineering or a related field
- Master's degree in Electrical Engineering or a related field
- PhD in Electrical Engineering or a related field
- 12+ years of work experience (for Bachelor's degree)
- 8+ years of work experience (for Master's degree)
- 5+ years of work experience (for PhD)
- 5+ years of experience in package layout or advanced PCB/package implementation
- Prior experience working with high-speed routing, power distribution networks (PDN), and package layout design principles
- Experience with industry-standard EDA tools for package layout and design
Desired Qualifications
- Experience leading or mentoring layout engineers or small technical teams
- Proficiency with Cadence APD+ or equivalent package layout tools
- Experience with ASIC package layout implementation, including high-speed interfaces and complex escape routing
- Prior experience with SI/PI considerations and collaboration with cross-functional engineering teams
- Experience working with vendors or outsourced layout resources
- Experience with scripting languages such as Python, Perl, or TCL
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