Head of Test Development Engineering
$220,000–$280,000 year
HybridSan Jose, California, United States
Job Summary
Lead end-to-end test architecture, infrastructure, and methodology from pre-silicon to post-silicon, bridging chip designs with high-volume automotive-grade silicon testing. Own early engagement with architecture, DFT, and security teams to establish ATE and SLT test strategies ensuring debug capability. Deliver manufacturing test programs from NPI bring-up through high-volume production for high-speed Ethernet switches and PHYs, managing test labs, OSATs, and vendor engagements for testers and probe cards. Ensure robust signal integrity and power/performance standards across wafer, final, and system-level test stages.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering or a related technical field
- 12+ years of experience in fabless semiconductor operations, specifically for complex, high-performance SOCs or networking ICs
- Expert in ATE 93K platform and Smartest, test method libraries and design of test hardware with robust SI/PI for wafer and final test
- Expertise with iJTAG, Scan (SSN), MBIST, Sensor, SerDes, LSIO/HSIO testing, security fusing and test automation for multi-site (x8, x16) parallel testing
- Expert in SLT testing using bare-metal, functional DVFS and benchmark testing and expert in multi-site handler automation framework and test log standards
- Experience with Analog characterizing high-speed communication chips on ATE and System to ensure all IO parameters are characterized and tested
- Experience defining DFT/DFM/DFD requirements for Ethernet PHY and Switch products and experience with scan and memory dump for debug
- Experience navigating the Automotive electronics ecosystem, including IATF 16949, ISO 26262, Safe launch and PPAP (Production Part Approval Process)
- Understanding of high-bandwidth data-path products (Ethernet, Switching, or high-speed SerDes)
- Expert level experience with ATE and SLT test hardware, test program development, high speed IO analog characterization and test automation
- Understanding of product life cycle from concept to end of life and leading pre-silicon review and readiness to enable seamless post-silicon bring-up
- The position is based in San Jose, CA
Desired Qualifications
- Experience with simulation, pattern generation, and pattern conversion
- Experience delivering high speed SerDes products to Tier-1 automotive OEMs
- Experience negotiating with and managing hardware vendors and OSATs
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