Hardware Technical Program Manager
$200,000–$240,000 year
On-siteSan Jose, Texas, United States
Job Summary
Own the silicon schedule from architecture freeze through tapeout, bring-up, and production release, driving weekly execution cadence and maintaining a single source of truth for status and dependencies. Coordinate handoffs across architecture, RTL, DV/emulation, DFT, physical design, and foundry partners while managing critical dependency chains for IP, PDK, and EDA versions. Surface early risks with quantified schedule impacts and facilitate PPA, schedule, and scope tradeoffs, documenting decisions and holding owners to closure. Interface with supply chain, OSAT, and legal teams for export compliance, deliver executive reporting across distributed teams, and track NRE and mask budgets against program needs.
Required Qualifications
- B.S. in Electrical/Computer Engineering, Computer Science, or equivalent
- M.S. or MBA
- 7+ years in semiconductor/hardware engineering or program management
- at least 2 full SoC/ASIC programs taken from concept through tapeout and silicon bring-up
- Working fluency in the chip design flow: RTL, functional verification and coverage closure, DFT, synthesis, PnR, STA, physical signoff (DRC/LVS/IR/EM), GDSII handoff, and post-silicon validation
- Demonstrated ability to build and defend a bottoms-up schedule with critical path analysis and dependency mapping
- Track record influencing without authority — earning the technical credibility to push senior engineers on commitments and dates
- Strong written and verbal communication; able to run a room of principal engineers and an exec review with equal effectiveness
- Hands-on with program tooling: Jira, Confluence, MS Project/Smartsheet, and familiarity with the Synopsys/Cadence/Siemens EDA ecosystem
Desired Qualifications
- M.S. or MBA a plus
- Prior hands-on engineering experience in design, DV, or physical design before moving to program management
- Experience on advanced or FinFET nodes (16/12/7nm or more advanced) and direct foundry engagement (TSMC preferred)
- Familiarity with AI/ML accelerators, dataflow or novel compute architectures
- Experience managing emulation/FPGA prototyping programs and pre-silicon software enablement timelines
- Exposure to package/board co-design programs (FC-BGA, WLCSP) and OSAT coordination
- Experience with EVK/reference board programs and customer/FAE enablement schedules
- Familiarity with quality and compliance frameworks relevant to the target market (automotive, industrial, or security certifications)
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