Hardware Engineer, RTL/PD
$200,000–$285,000 year
On-siteLondon, England, United Kingdom or New York City, New York, United States
Job Summary
Own RTL from microarchitecture to tapeout by writing synthesizable SystemVerilog, creating specifications, and collaborating with verification engineers to close coverage using conventional and formal methods. Drive the full backend design flow, including floorplanning, detailed place and route, CTS, timing closure, DFT insertion, and LVS/DRC to deliver fab-ready GDSII. Participate in design reviews to shape architecture decisions and create signoff checklists for tapeout, supporting post-silicon characterization bring-up as needed. This role requires at least three prior tapeouts and experience working with architects where specifications are developed in parallel.
Required Qualifications
- Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route
- At least three tapeouts in your background, from any node and any company size
- Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
- Strong debugging instincts across simulation, waveforms, and formal counterexamples
- Ability to work directly with architects, design verification, and fab representatives
Desired Qualifications
- Experience at an AI chip company where design, verification, and PD were tightly coupled
- Familiarity with RISC-V or other open ISAs
- Experience with AI-assisted RTL or EDA tooling in your design workflow
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