FPGA Verification Engineer Level 5 - Linthicum
$185,900–$278,900 year
On-siteLinthicum, Maryland, United States
Job Summary
Lead FPGA verification efforts across multiple programs by defining plans, implementing a VUnit-based framework, and establishing CI/CD pipelines for nightly regression and coverage reporting. Write VHDL test suites, develop functional-coverage models, and perform root-cause analysis on simulation failures while coordinating hardware bring-up and lab validation. Deliver coverage and traceability reports to ensure metrics meet program exit criteria before design handoff. Mentor junior engineers, coach on verification best practices, and promote design-for-verification throughout the organization. Partner with design, systems, and software teams to guarantee complete coverage and participate in SRR, PDR, CDR, and TRR reviews. Identify technical risks, define mitigation plans, and enforce adherence to internal FPGA development processes and DoD security standards.
Required Qualifications
- Bachelor's degree with 12 years of experience, a master's degree with 10 years of experience or a PhD with 7 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields
- Proficiency in hardware description languages (e.g., SystemVerilog, Verilog, VHDL)
- Knowledge and hands-on experience with VUnit
- Digital subsystem, ASIC, FPGA and/or digital board development experience and knowledge essential
- Must be able to obtain and maintain Secret or Top-Secret level security clearance, per business requirements
- Experience developing test plans, participating in reviews, test development and RTL debug
- Must be able to mentor and coach early career Engineers as needed
- Must be able to effectively lead and coach others
- Must be able to obtain and maintain a TS/SCI clearance w/SAP
Desired Qualifications
- Advanced Degree with at least 10+ years of professional experience in related industry
- Active DoD Top Secret Clearance or higher with SAP Access and or SCI eligibility
- Experience with Verification IP integration and/or development
- Experience with a coverage-driven verification methodology from planning through closure
- Experience in creating comprehensive documentation of test cases, verification plans/methods, and test results for review and future reference
- Development of scripts and use of verification tools like VUnit or proprietary frameworks to streamline and automate verification processes
- Knowledge of industry standard bus or I/O interfaces
- Experience with VHDL Assertions
- FPGA/ASIC design and/or development process experience
- Experience with scripting languages (Python, Tcl, Makefile)
- Knowledge of digital signal processing
- Knowledge of working with Xilinx and MicroChip FPGAs (Kintex, Zynq ultrascale+, RTG4, etc)
- Effective communication with systems and software teams for requirements, ICDs, handoffs, etc
- Able to work effectively within a development team to understand system level inter-dependence and design constraints
- Active Top Secret clearance a plus
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