FPGA Verification Engineer Level 3/4 - Linthicum
$119,600–$179,400 year
On-siteLinthicum, Maryland, United States
Linthicum, Maryland, United StatesOn-siteFull Time$119,600–$179,400 yearAssociates DegreeEnterprise
Full TimeAssociates DegreeEnterprise
Job Summary
Perform functional verification of register transfer level (RTL) code for complex FPGAs at block and SOC levels using VUnit, developing testbenches, tests, verification IP, and coverage models. Create verification plans based on design specifications, analyze simulation failures to identify root causes, and collaborate with designers to resolve issues. Automate regression testing to ensure new changes do not break existing functionality while working closely with design and other verification engineers.
Required Qualifications
- U.S. citizen
- Ability to obtain and maintain a DoD Secret or Top-Secret Clearance per business requirements
- Bachelor's degree with 5 years of experience; or a master's degree with 3 years of related experience; or a PhD with 0 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields
- 3 years of experience with FPGA verification using VUnit
- Experience with the use of various FPGAs or the development of HDL (Verilog, SystemVerilog and VHDL) code within the corresponding IDE
- Experience developing test plans, participating in reviews, test development and RTL debug
- Proficiency in hardware description languages (e.g., SystemVerilog, Verilog, VHDL)
- Familiarity with industry-standard tools (e.g., Synopsys, Mentor Graphics)
- 3+ years of experience with FPGA verification using VUnit
- Digital subsystem, ASIC, FPGA and/or digital board development experience and knowledge essential
- Good communication skills, strong interpersonal skills, and good oral and written presentation skills
- Must be able to mentor and coach early career Engineers as needed
- Ability to operate in a team environment and collaborate across the different teams as required to accomplish the design goals
- Ability to work effectively within a development team to understand system level inter-dependence and design constraints
Desired Qualifications
- Active DoD Top Secret Clearance or higher and/or SCI eligibility
- Experience with data structures, object-oriented programming languages and concepts
- Experience with Verification IP integration and/or development
- Experience with a coverage-driven verification methodology from planning through closure
- Experience in creating comprehensive documentation of test cases, verification plans/methods, and test results for review and future reference
- Knowledge of industry standard bus or I/O interfaces
- Experience with SystemVerilog Assertions (SVA)
- Experience with VHDL Assertions
- FPGA/ASIC design and/or development process experience
- Experience with scripting languages (Bash, Perl, Python, Tcl, Makefile)
- Knowledge of digital signal processing
- Knowledge of working with Xilinx and MicroChip FPGAs (Kintex, Zynq ultrascale+, RTG4, etc)
- Effective communication with systems and software teams for requirements, ICDs, handoffs, etc.
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