FPGA Verification Engineer, Air Vehicles
$123,000–$171,000 year
On-site · Costa Mesa, California, United States
Job Summary
Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs; develop verification plans with traceability to system and hardware requirements; author SystemVerilog Assertions for protocol compliance and design intent checks; build functional coverage models and drive code coverage analysis to closure; develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs; establish and maintain regression suites, tracking coverage metrics and verification progress; debug failures using waveform tools and simulation logs at the HDL and system level; collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement; support hardware validation and board bring-up on target platforms; ensure verification meets DO-254 and relevant safety standards; author verification closure reports and coverage analysis summaries.
Required Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
- 2+ years of experience in FPGA/ASIC verification
- Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches
- Object-oriented programming principles
- Industry simulators (Questa, VCS, Xcelium, or Vivado)
- Git-based collaborative workflows including code review
- Linux development environments
- Strong communication and teamwork skills
- Eligible to obtain and hold a U.S. Secret security clearance
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