FPGA Development Tools Engineer – Synthesis

FPGA Development Tools Engineer focused on synthesis to advance RTL-to-gate-level transformations. Responsible for designing, implementing, and optimizing synthesis algorithms, contributing to the FPGA compiler flow (integration with placement, routing, and timing), and improving QoR (performance, power, area) through synthesis-driven techniques. Performs RTL analysis, collaborates cross-functionally with architecture, STA, placement, routing, and validation teams, and engages in debugging and validation of synthesis results. Develops tooling and automation (scripting) to improve synthesis flows and productivity. Requires strong RTL design experience (Verilog/SystemVerilog/VHDL), a solid software engineering background, and familiarity with EDA/CAD concepts;Bachelor’s/Master’s (PhD encouraged) in related fields. Compensation is CAD with base salary plus performance-based incentives; Canada location with Toronto, Ontario as primary site. US visa sponsorship not indicated; Canadian work experience not required for this role. Why Join Altera includes building core synthesis tech for next-gen FPGA platforms and collaboration with world-class engineers.