Founding Hardware Engineer
On-site · San Francisco, California, United States
Job Summary
Founding Hardware Engineer responsible for leading hardware engineering efforts across multi-agent platform and domain-specific hardware knowledge base. Drive technical direction and shape product roadmap with real-world context. Integrate into customer pipelines across RTL, PD, and architectural stages; track trends in semiconductor design and AI-assisted design automation; create internal benchmarks and datasets to evaluate system performance across RTL, PD, and architectural use cases. Requires hands-on experience in semiconductor/EDA environments, proficiency with SystemVerilog/Verilog, RTL/architecture development, and experience with leading-edge tapeouts (7nm+). Strong scripting skills (Python, Bash) and familiarity with EDA tools (Genus, Innovus, Tempus, Mentor Calibre, Synopsys IC Compiler) are expected. Preferred experience includes AI-for-chip-design initiatives and knowledge of DFT, power optimization, IP development teams (PCIe, PHY, NoC, CPU subsystems). Candidates with advanced degrees in EE/CE or related fields are encouraged.
Required Qualifications
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related discipline (interns may be considered for their flair)
- Hands-on experience in a semiconductor or EDA environment (e.g., NVIDIA, AMD, Intel, Synopsys, Cadence), 1+ years of full-time experience required, 3+ years preferred
- Proficiency in scripting (Python, Bash) and experience with automation or tooling for design verification or integration
- SPECIALTY: DI (Design Integration, RTL, Architecture)
- Proven track record of developing architectures and RTL for hardware blocks or IP
- Experience with SystemVerilog, Verilog & SoC design methodologies
- SPECIALTY: PD (Physical Design)
- Part of leading edge tapeouts (7nm or smaller). Worked on at least one of synthesis, floor planning, place-and-route, physical verification, and timing
- Familiar with one of Genus, Innovus, Tempus, Mentor Calibre, Synopsys IC Compiler, or other relevant EDA CAD tool (and associated TCL)
- Preferred Experience: Experience on AI-for-chip-design initiatives (e.g., at Synopsys, NVIDIA, GoogleDeepMind)
- Understanding of DFT, power optimization techniques, or low-power design flows
- Experience on an IP development team, developing PCIe, PHY, LPDOR, MemoryControllers, NoC, CPU subsystems, or similar
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