Formal Verification Engineer
$500,000–$2,200,000 year
On-siteBengaluru, Karnataka, India
Job Summary
Develop, maintain, and execute formal property checks, including assertions, assumptions, and coverage, for complex SoC components such as interconnects, memory subsystems, power management, and security IPs. Perform block-level and chip-level formal verification using industry-standard tools like JasperGold, VC Formal, or Questa Formal. Collaborate with RTL and design verification teams to debug counterexamples, resolve design issues, and achieve formal verification closure. Define and enhance formal verification methodologies, reusable frameworks, and best practices across projects. Own Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) verification by identifying synchronization issues, validating multi-bit crossings, and ensuring safe clock domain interactions. Contribute to verification planning, coverage analysis, closure tracking, and tape-out sign-off activities. Identify RTL design bugs through formal analysis and provide effective root-cause analysis. Drive the adoption of Formal Property Verification (FPV), Sequential Equivalence Checking (SEC), and connectivity verification techniques.
Required Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related field
- 3–8 years of hands-on experience in formal verification of digital hardware or SoC designs
- Strong expertise in Formal Verification, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) verification
- Proficiency in SystemVerilog Assertions (SVA) and formal property specification methodologies
- Hands-on experience with commercial formal verification tools such as JasperGold, VC Formal, Questa Formal, or similar solutions
- Strong understanding of RTL design, digital logic, SoC architecture, and standard bus protocols such as AXI, AHB, and APB
- Experience debugging formal verification failures and analyzing counterexamples effectively
- Excellent analytical, debugging, and problem-solving skills
- Strong communication skills with the ability to collaborate across cross-functional engineering teams
Desired Qualifications
- Experience with Lint analysis and static design verification methodologies
- Exposure to UPF (Unified Power Format) and low-power verification techniques
- Familiarity with formal verification methodologies for low-power and power-aware designs
- Knowledge of verification automation using scripting languages such as Python, Perl, or Shell
- Experience participating in complete SoC verification and tape-out cycles
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