Formal Verification - DV
On-site · San Jose, California, United States
Job Summary
Formal Verification Engineer role within the ASIC Design Verification team at Etched. Lead formal verification across custom IP, interface IP, and SoC subsystems for ASICs, collaborating with architects, RTL designers, DV engineers, emulation and software/firmware teams. Define verification strategy, develop plans, build reusable environments using SystemVerilog Assertions and reference models, drive proof convergence, and contribute to formal sign-off methodology. Candidates should have 5+ years in design verification with hands-on formal verification experience, strong SystemVerilog/SVA skills, experience with JasperGold, VC Formal, or Questa Formal, and a track record of debugging complex RTL and subsystem verification. The role emphasizes collaboration across multiple teams, optimization of verification workflows, and a startup-paced environment. Benefits include relocation support to San Jose, medical/dental/vision, housing subsidy, daily office meals, and wellness programs. Location is in-person at San Jose (Santana Row), CA, USA.
Required Qualifications
- 5+ years of design verification experience
- Significant hands-on formal verification experience on complex digital designs or shipping silicon
- Strong proficiency with SystemVerilog and SystemVerilog Assertions
- Experience with Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal
- Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces
- Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models
- Experience collaborating across architecture, RTL design, UVM DV, emulation, software, firmware, and vendor teams
- Proven debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports
- Willingness to work in a fast-paced startup environment and take ownership of high-impact verification problems
- Formal verification of systolic arrays, DMA engines, NoCs, memory subsystems, PCIe, Ethernet, AXI/AMBA, CPU interfaces, or low-power controllers (preferred)
- Scripting in Python, TCL, Perl, or similar for automation and regression management (preferred)
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